A highly integrated power-down detection circuit application

I believe that everyone will encounter such a situation. When you are typing a document or a piece of code, you have a power outage, I rub..., my code..., my drawings..., I just wrote a good article. .... However, similar situations are encountered in embedded systems, which often result in embedded system data, missing programs, inoperability, and even damage to the storage system. For the embedded system of the core board, the data is not lost under abnormal power failure, and the stability is fundamental. This article introduces a method based on CAT706 that can detect abnormal power loss and save data with a small amount of power stored in the capacitor to prevent memory damage and data loss.

I. Overview

First quote a WeChat article "The boss said: You go to the job, I went to the building! A disaster caused by the SD card"

In the first half of last year, our company undertook the elevator advertising display project of a large advertising company. This product uses Freescale's IMX6 series chip as the main control CPU, with media human-machine touch interaction, media delivery, remote upgrade, video recording. Monitoring and other functions. One of the most important functions is the monitoring and saving function. Due to the low price of the customer, we have chosen the SD card as the storage medium for the recording data.

Unexpectedly, the disaster came down half a year later. The 10K machine shipped six months ago has a 10% damage rate every month. 90% of the damaged machines are damaged by the SD card! The customer not only asks us to compensate for the loss of the SD card, extend the warranty period, but also threatens to terminate the cooperation within one month without resolving. The customer is the sole big customer of the boss. We are not far from losing this customer. The boss even put down the swear words: I won't solve it within a month, you jumped, I jumped.

After careful inspection, the cause of the SD card damage is caused by the power-on and power-off of the device.

So we adopted the following scheme. The core of the solution is the power-down detection circuit and the super capacitor to continue the power supply circuit. The power-down detection circuit is a relatively complicated comparison circuit that is built out by an op amp. Since it is complicated, it is not shown here. Figure 1 shows the charging and discharging circuit of the super capacitor. Adding this circuit can continue to maintain the power for 2 seconds after the power is turned off, so that the CPU can complete the protection processing after power failure.

Figure 1 super capacitor charging and discharging circuit

The above-mentioned case ending method is to use the operational amplifier to build a power-down detection circuit that is more complicated and prone to problems. Here, we recommend a highly integrated power-down detection circuit.

Second, the function profile:

Figure 2 shows the internal block diagram of the CAT706 chip. CAT706 integrates a variety of functions, powerful, easy to use, this time only focus on its internal power-down detection.

Figure 2 internal functional block diagram

Since the internal block diagram is very simple, it can be easily analyzed that the following four conditions can cause the microcontroller to reset or interrupt:

• When the VCC power supply does not meet the requirements, it can cause the RESET reset output;

• The MR pin can manually reset the RESET output;

• Watchdog WDI does not feed the dog in time to cause WDO reset output;

• The power-down detection input PFI can cause the PFO to interrupt the output.

The role of the above four functions on the embedded system is as follows:

• It can ensure that the single-chip microcomputer works when the VCC power supply is stable, and the reset output ensures the stable operation of the system when it is unstable;

• Can manually control the microcontroller reset operation;

• Watchdog real-time monitoring system to prevent system crashes;

• Monitor the power supply system in a timely manner to allow the system to process data quickly.

This article is mainly for the protection of the fourth point to detect accidental power failure.

Third, the typical application

PFI is equivalent to the positive input of a voltage comparator. If the PFI voltage is higher than 1.25V, the PFO will output a high level. If the PFI voltage is lower than 1.25V, the PFO will output a low level. In this way, the high voltage of the front end can be divided and input through the PFI as an input, so that the power failure of the front end can be detected in advance.

Figure 3 shows the typical application circuit and timing diagram of the CAT706. The schematic is relatively simple and easy to understand, and the theoretical waveforms of the various parts after power-down and power-on are drawn.

Under normal circumstances, the power supply of the system is reduced from the front-end mains isolation to a relatively high DC voltage (such as 12V), and then stepped down to the voltage required by the system (such as 5V/3.3V). As shown in FIG. 3, it is a power-down detecting circuit for detecting a 12V DC voltage of the front end.

Figure 3 Typical application circuit and timing diagram

The 5V output when the 12V is powered on will charge the large capacitor. In the figure, a resistor is connected in series to limit the current. When the power is turned off, the capacitance of the capacitor will be directly discharged to the back load through the adjacent Schottky diode.

Since there is a time difference between the 12V power-down and the 5V/3.3V power-down completion, the 12V power-down condition can be detected in advance to make the MCU enter Interrupt to take a series of countermeasures against power-down, and before the 5V/3.3V power-down is completed. The operation is completed, as shown in the time T in the figure, and the time T is related to the capacitance value of the red circle in the figure. The larger the capacitance value, the longer the time T (if necessary, the farad capacitor can be considered); and the power failure is detected. The closer the signal is to the front end of the main power supply, the better.

In order to increase the maintenance time T after power-off, not only the storage capacitor value can be increased to achieve the purpose, but also the power-down detection signal can be moved to the front end, for example, the power-down detection is moved to the front-end 220V mains or front end. High voltage, there is also a period of time when the mains power is turned off to 12V power down, so that the maintenance time T after power failure can be indirectly increased.

As shown in FIG. 4, the power-down detecting circuit for detecting the front end voltage is shown. The power-down signal is processed in advance to increase the voltage maintenance time after power-down.

Figure 4 front end power failure detection circuit

Taking the position of the farad capacitor shown in Figure 3, it can be seen that as the voltage after power-down is maintained, the voltage drop on the capacitor may gradually affect the operation of the back-end system. To this end, the large capacitor charge and discharge circuit can be moved to the high voltage part of the front end, or the step-down circuit can be divided into two or three sections of step-down connection, so that only the placement position of the large capacitor is moved to the front end. It can ensure that the working voltage of the main system remains stable during the period when the power is off. Change the placement position of the large capacitor as shown in Figure 4.

Fourth, the actual measurement analysis

For the calculation of the CAT706 principle and the calculation of the actual effect waveform in the previous section, we have made the following hardware circuit construction, and the hardware circuit is built for Figure 3. The hardware shown in Figure 5 is built using a hole plate to test the actual input supply voltage waveform, the output voltage waveform, and the waveforms of the PFO and RST pins.

Figure 5 physical map

As shown in Fig. 6, waveform 1 is the input 12V voltage waveform, waveform 2 is the output 5V voltage waveform, waveform 3 is the voltage waveform of the reset pin, and waveform 4 is the voltage waveform of the PFO pin. In the figure, the output is discharged at a constant current of 10 mA.

Figure 6 test waveform

When the input 12V rises, the DCDC power supply will start to output 5V, and then the 12V rises. If the voltage divider value is greater than the input threshold of PFI, the PFO will immediately output a high level, and the reset pin detects that the 5V voltage is normal. After a while, the system will be reset and the system will start working.

When the input 12V unexpected power-off falls, the PFO will immediately output a low level when the voltage divider value on the PFI pin is lower than the threshold. The low level of this PFO will interrupt the system master and inform the system that the system should be powered off unexpectedly. Data is processed to prevent data loss. The test waveform in the figure is simulated with a constant current load of 10 mA. It can be seen from the figure that there is a processing time of 244 ms from the detection of the unexpected power failure to the system reset stop. This time has a great relationship with the capacitance of the DCDC output. The larger the capacitance value, the longer the data processing time. The figure is measured with a capacitance of 2200μF and a constant current of 10mA. In the actual processing, the power-down master should detect that the power-consuming peripherals such as the LCD screen should be disconnected immediately, and only the power supply of the main control part can be maintained.