IC integrated circuit basics

IC integrated circuit basic concept

1. Which types of ICs can be divided according to the process and structure?

ICs can be divided into three categories depending on the process and structure:

1 semiconductor IC or monolithic IC, 2 film IC, can be divided into two types: thick film circuit, thin film circuit; 3 hybrid IC (Hybrid IC) according to device structure type classification: bipolar integrated circuit, metal - An oxide-semiconductor (MOS) integrated circuit.

2. What technical indicators are used to describe the level of integrated circuit process technology?

Five technical indicators describing the level of integrated circuit process technology: integration, feature size, chip area, wafer diameter, package.

3. Why are the standards for dividing the scale of integrated circuits between digital ICs and analog ICs different?

Because there are many repeating units in a digital IC, there are basically no repeating units in an analog IC.

4. Who invented the integrated circuit in which year? Which one won the Nobel Physics Award?

In 1958, a research team led by Texas Instruments scientist Clair Kilby developed the world's first integrated circuit, and the results were published in 1959. Received the 2000 Nobel Physics Award.

5. Why do the networks that realize social information and their key components, whether they are various computers and/or communication machines, are based on microelectronics?

Because its core component is an integrated circuit. Almost all traditional industries combined with microelectronics technology and intelligent transformation with integrated circuit chips can rejuvenate the traditional industry. The upgrading of electronic equipment is based on the advancement of microelectronics technology, and the degree of its Smart depends on the degree of "intelligence" of the integrated circuit chip and the degree of use.

6. What are the ways to increase integration?

Improve micro-machining technology; increase chip area; wafer diameter; simplify circuit structure.

7. In what direction will the 21st century silicon microelectronics chip continue to move forward?

1) The feature size continues to scale down and continues to develop at a high speed along Moore's Law;

2) On-chip chip (SOC): Microelectronics is developed from integrated circuits to integrated systems (IS);

3) Give the microelectronic chip more "Aura": micro-mechanical electronic systems (MEMS) and micro-optical motor systems (MOEMS), biochips;

4) Silicon-based quantum devices and nanodevices.

8. Give a brief explanation of the following English words or abbreviations:

IC integrated circuit (IC)

SSI Small Scale IC (Small Scale IC, SSI)

MSI Medium Scale IC (MSI)

LSI large scale integrated circuit (Large Scale IC, LSI)

VLSI Very Large Scale IC (VLSI)

ULSI Ultra Large Scale IC (ULSI)

GSI Gigantic Scale IC (GSI)

Wafer wafer, Foundry standard process plant or IDM integrated device manufacturer (IDM—Integrated Device Manufactory Co.)

IP core intellectual property core, fabless co. production line company (integrated circuit design company), chipless co. chipless company (developing intellectual property core company), mp microprocessor, DSP digital signal processing, E2PROM electrically erasable programmable Read-only memory, Flash flash memory, A/D analog-to-digital conversion, D/A digital-to-analog conversion, SOI insulating silicon film (Silicon on Insulator), SOS sapphire substrate epitaxial silicon structure (SOS-Silicon on Sapphire structure)

IC process

1. What are the main processes of the silicon integrated circuit manufacturing process?

1) Graphics conversion: transfer the pattern designed on the mask (similar to the photographic film) to the semiconductor single wafer; 2) Doping: doping various impurities at the required position according to the design requirements, forming Transistors, contacts, etc.; 3) Film formation: Films made of various materials.

2. What is the purpose of the plate making? Pattern Generator (PG-pattern generator) What is the equipment used to do?

Plate making is the reduction and repetition of graphics through the graphics generator. After designing the layout of the integrated circuit, the designer gets a set of standard plate-making data, which is sent to the graphics generator (a plate-making device). The PG-pattern generator is based on the data. The layout results of the design are layered and transferred to the reticle (the reticle is a high-quality glass plate coated with photosensitive material), and this process is called initial shrinkage.

3. What are the steps in the graphics conversion process?

Photolithography and etching processes.

4. Why is lithography (including etching) a key process technology for processing integrated circuit micro-pattern structures? What are the steps in the lithography process?

Lithography is a key process technology for processing integrated circuit micro-pattern structures. Generally, the more lithography times, the more complicated the process. On the other hand, the finer the lines that lithography can process, the higher the process line level. The lithography process is done to open the window on the entire wafer. The process is as follows:

1) base film (HMDS adhesion promoter, hexamethyldisilane (HMDS)), 2) photoresist, 3) pre-bake, 4) exposure, 5) development, 6) hard film, 7 Etching: dry etching (Dry Etching), 8) stripping: chemical method and dry stripping.

5. Explain the meaning of the three elements of lithography.

Three elements of lithography: photoresist, reticle and lithography machine.

6. What are the characteristics of positive gel (photodecomposition) and negative gel (photopolymerization)? Which photoresist is commonly used in VLSI processes? Is the AZ-1350 series positive or negative?

Positive glue: soluble after exposure, negative gel: insoluble after exposure.

The main advantage of positive glue is its high resolution, which is usually used in VLSI processes. The AZ-1350 series is a positive glue.

Photoresist-photoresist; positive and negative: positive and negative; mask-photomask; lithography machine-lithography machine.

7. What are the common lithography methods? What are the advantages and disadvantages of contact and proximity optical exposure technology?

1) Contact lithography: high resolution, but easy to cause damage to the reticle and photoresist film.

2) Proximity exposure: There is a small gap (10~25mm) between the silicon wafer and the mask, which can greatly reduce the damage of the mask and the resolution is low.

3) Projection Exposure Stepper: An exposure method that uses a lens or mirror to project a pattern on a mask onto a substrate, the most widely used exposure method.

8. Explain the type and role of graphic etching techniques.

Wet etching: A method of etching by chemical reaction using a liquid chemical reagent or solution.

Dry etching: mainly refers to the use of ions or radicals in the plasma generated by low-pressure discharge (molecules, atoms and various atomic groups in an excited state) to chemically react with materials or achieve physical effects by bombardment and other physical effects. The purpose of the eclipse.

9. How many doping processes are there? What kind of impurities do you need to do to obtain a P-type region on an N-type substrate? What kind of impurities do I need to incorporate in order to obtain an N-type region on a P-type substrate? What are the advantages and disadvantages of thermal diffusion and ion implantation?

The doping process is divided into thermal diffusion doping and ion implantation doping. In order to obtain a P-type region on the N-type substrate, it is necessary to dope the boron impurity of the III-valent element. In order to obtain an N-type region on a P-type substrate, a V-valent element phosphorus and arsenic impurity are doped. The so-called thermal diffusion doping is to use the diffusion movement of atoms at high temperature to diffuse impurity atoms from a high concentration impurity source into silicon and form a certain distribution. The process is relatively simple, but the doping concentration control is poor in accuracy and positional accuracy is also poor. Ion implantation is a doping technique in which impurity ions having a very high energy are incident into a semiconductor substrate. The doping depth is determined by the energy and mass of the implanted impurity ions, and the doping concentration is determined by the number (dose) of implanted impurity ions.

The ion implantation technology is replacing the thermal diffusion doping technology with its advantages of precise doping concentration control and accurate position, and has become the main technology for doping in the VLSI process. But expensive equipment and annealing processes are required. The lattice of the silicon structure is damaged due to the impact of the high energy particles. In order to recover the lattice damage, annealing treatment is performed after ion implantation. Depending on the amount of impurities implanted, the annealing temperature is between 450 ° C and 950 ° C. When the doping concentration is large, the annealing temperature is high, and vice versa. At the same time as annealing, the incorporated impurities are simultaneously redistributed into the silicon body, and if necessary, subsequent high temperature processing is performed to obtain the desired junction depth and distribution.

10. What method is usually used to make SiO2 film?

Thermal oxidation method: dry oxygen oxidation, water vapor oxidation, wet oxygen oxidation, dry oxygen-wet oxygen-dry oxygen (referred to as dry and wet dry) oxidation method; hydrogen-oxygen synthesis oxidation; chemical vapor deposition method; thermal decomposition deposition method;

Sputtering method

11. Two examples of application of physical vapor deposition and chemical vapor deposition in IC processes are described separately.

CVD (CVD-Chimical Vapor Depositiom) is a process of depositing a thin film material on a substrate by chemical reaction of gaseous substances. It has low deposition temperature, easy control of film composition and thickness, uniformity and repeatability, and step coverage. A series of advantages such as excellent, wide application range and simple equipment. The more common CVD films include: silicon dioxide (commonly referred to directly as oxide layer), silicon nitride, polysilicon, refractory metals and silicides of such metals.

PVD (Physical Vapor Deposition) is mainly a physical process rather than a chemical process. This technique generally uses a blunt gas such as argon. After argon ions are accelerated in a high vacuum to hit the sputter target, the target atoms can be splashed one by one and the splashed material (usually aluminum, titanium) Or its alloy) deposited as a snow flake on the surface of the wafer.

12. What is the field and active area?

A very thick oxide layer, located on the chip where there is no transistor or electrode contact, called the field. The active area is the area where the transistor is fabricated.

13. What steps are included in the post-process of the IC?

The post-process includes: dicing, adhesive sheet, pressure-welded lead, packaging, finished product testing, aging screening, printing and packaging.

14. Explain the meaning of the following English words or abbreviations:

PG pattern generator, Stepper projection exposure, UV ultraviolet (Ultraviolet), DUV deep ultraviolet (Deep), EUV extreme ultraviolet (Extra), CVD chemical vapor deposition, PVD physical vapor deposition, APCVD atmospheric pressure Atmosphere Pressure, LPCVD low pressure chemical vapor deposition (Low), PECVD Plasma Enhanced Chemical Vapor Deposition, DIP dual-in-line package, PGA Grid Array Package, BGA Ball Grid Array, SOP Small Out-line, SOJ J-Lead Small Outline Package (Small Out-Line) J-Leaded Package), QFP quad flat package, PLCC plastic J type with leaded chip carrier (SMD), SMT surface mount package (Surface Mounted Technology).

Basic manufacturing process of integrated circuits

1. There are several types of isolation technology for bipolar ICs.

The pn junction isolation and isolation of the dielectric.

2. Standard buried collector isolation process SBC—Standard Buried Collector Process

3. What are the characteristics of pn junction isolation technology? What is the role of N+ buried layer diffusion?

The high-impedance characteristics of the reverse-biased pn junction are used for electrical isolation. It requires that the isolation trench must be connected to the lowest potential of the circuit. Since the transistor in the integrated circuit is a three-junction four-layer structure, the terminals of each component in the integrated circuit are taken out from the upper surface and interconnected on the upper surface, in order to reduce the transistor collector. The series resistance rCS reduces the influence of the parasitic PNP tube, and an N+ buried layer is required between the epitaxial layer of the fabricated component and the substrate to provide a low resistance path of the IC. The effect of the N+ buried layer diffusion is to reduce the series resistance of the collector and reduce the influence of the parasitic PNP tube. In order to further reduce the collector series resistance rCS collector contact area plus phosphorus penetration diffusion (should be performed before the base region is diffused).

4. How many masks are required to make an NPN tube on an isolated island? Write the names of the masks in the order of the process.

A minimum of six masks are required.

First photolithography—N+ buried layer diffusion, second photolithography—P+ isolation diffusion, third photolithography—P-type base diffusion, fourth photolithography—N+ emitter diffusion, fifth photolithography— Lead contact, sixth lithography - metallization interconnect: reverse engraved aluminum.

5. What are the characteristics of the isolation technology?

The pass isolation technique reduces the actual width of the isolation trench.

6. Briefly describe the P-well silicon gate CMOS process flow. What is the purpose of each photolithography?

1. Photolithography I---well region lithography, engraving the well region injection hole

2. The well region is injected and advanced to form a well region.

3, remove SiO2, long thin oxygen, long Si3N4

4, light II - active area lithography

5. Light III---N tube field lithography, N tube field injection, to increase the field to open VTF, reduce latch-up effect and improve well contact.

6, long field oxygen, bleaching SiO2 and Si3N4, and then long gate oxide layer.

7. Light IV---p tube field lithography (using negative version of light I), p tube field injection, adjusting the turn-on voltage of the PMOS tube, and then growing polysilicon.

8, light V---polysilicon lithography, forming polysilicon gate and polysilicon resistor

9. Light VI---P+ area lithography, P+ area implantation. The source and drain regions of the PMOS transistor and the P+ guard ring are formed.

10. Photo VII---N tube field lithography, N tube field injection, forming NMOS source and drain regions and N+ protection ring.

11, long PSG (phosphorus silica glass).

12. Photolithography VIII---Lead hole lithography. PGS reflux.

13. Photolithography IX---Lead hole lithography (reverse engraving AL).

14. Lithography X---pressure pad lithography.