A power module for supplying power to a radio frequency low noise amplifier in a monolithic millimeter-wave integrated circuit

Abstract: A power supply module for powering a radio frequency low noise amplifier (LNA) in a monolithic millimeter-wave integrated circuit (MMIC) is designed. The power module is integrated in the MMIC and uses a low-dropout linear regulator (LDO) to provide a stable, low-noise supply voltage. Due to the noise of traditional LDO structure, a novel LDO structure with a combination of voltage pre-regulation and RC low-pass filtering is designed to reduce circuit noise, and a fast start-up is proposed for the shortcomings of RC low-pass filter circuit startup. Circuit configuration. The circuit is designed and simulated by SMIC 0.18 μm CMOS process. The test results show that the input supply voltage is 5 V, the output voltage is adjustable within the range of 1 to 4.2 V, and the voltage output linearity regulation (LNR) is 8.2 mV/V. The load regulation ratio (LDR) is 83.3 μV/mA, and the noise integral of the output noise voltage within 1 kHz to 100 kHz is 34.94 μVrms, which satisfies the power supply requirements of the LNA.

0 Preface

With the application of millimeter-wave radar technology in automotive autopilot applications, automotive millimeter-wave radar has gradually developed toward high integration, high precision, and high reliability. From the current research situation and product reports, only a few companies are able to provide solutions for MMIC car radar, and technology research and development can not fully meet the needs of market applications. MMIC can integrate RF front-end transceiver circuits and low- and medium-frequency signal processing circuits. The RF LNA is applied to the receiving end of the millimeter wave signal. It not only amplifies the received weak RF signal, but also introduces as little noise as possible during the amplification process for the subsequent circuit to process the signal [1].

RF LNAs are sensitive to power supply noise and cannot share a power management unit (PMU) with other modules. Therefore, separate power supply modules are required. At present, LDO low noise optimization design is mainly divided into two aspects 0. The first aspect is shown in Figure 1. By changing the traditional LDO circuit structure and adding an RC filter network to reduce the circuit noise, this structure can effectively filter out the high-frequency noise of the pre-stage circuit, but its disadvantage is the need to connect the external capacitor. , added a chip pin. The second method does not change the circuit structure of the conventional LDO. Since the main source of noise is the bandgap reference (BG) and error amplifier (EA), the second method achieves low noise voltage by designing low noise BG and EA. Output. This method does not require off-chip capacitance and does not increase the chip area, but it is less effective in reducing high-frequency noise than the first method. This article adopts a new type of circuit structure, and also minimizes the output noise of BG and EA by optimizing the circuit design.

1 LDO overall circuit

Figure 1 shows the structure of the LDO circuit designed in this paper. It can be simply divided into three parts: pre-conditioning circuit, filter circuit, and post-regulation circuit [3].

M2 is a pre-adjustment tube. The voltage VI is output as the feedback voltage VFB through R1 and R2 in the RDAC module, and is compared with the bandgap reference voltage VBG by the error amplifier EA, and the control voltage VI is controlled by controlling the gate voltage of the M2. The purpose, because the noise mainly comes from BG, EA and R1, R2, so the voltage VI through the low-pass filter module, filter out high-frequency noise, and then through the amplifier AMP and adjust the tube M1 produces a low noise output VOUT [4]. The RS<7:0> 8-bit digital control signal controls the output voltage VOUT by changing the ratio of R1 and R2. C1 and R1 form a phase compensation network. By adjusting the position of the main pole of the circuit, the feedback loop has sufficient phase margin [5].

It can be seen from Equation (5) that the overall output noise power is significantly reduced after voltage pre-regulation and RC low-pass filtering [8].

2 Specific circuit design of each module 2.1 Bandgap reference source circuit

As shown in Fig. 2, BG is mainly composed of three parts, namely start-up circuit, bias current generation circuit and VBG generation circuit [9].

Among them EN is the control signal, when EN is 1, ENN is 0, M1- M5 is turned on, M5 will inject the electric current to the bias circuit, make it break away from degeneration to work normally, and when EN is 0, the circuit stops working . The bias current generation circuit generates a reference current through a combination of a current mirror and a resistor. These reference currents provide a reference current input for the amplifier.

The working mode of BG is to achieve the purpose that the voltage does not change with temperature by the mutual cancellation of the positive and negative temperature coefficients, and VBG can be expressed as formula (6).

By formula (6), formula (7) can be obtained, by increasing the product of mn can effectively reduce the noise.

2.2 Amplifier Circuit

Amplifiers in BG, pre-stage pre-regulation loops, and fast-start RC filter circuits all use a folded cascode structure. Its advantage is that under the condition of ensuring enough loop gain, the circuit has a faster response speed and the noise introduced by the circuit is moderate, within a controllable range. The specific circuit is shown in FIG. 3 .

The AMP in the post-regulation circuit uses a classic secondary op amp structure. Its advantages are high gain, low noise, and a relatively large output voltage swing [10].

The main noise sources of the folded cascode structure are M7-M8, M9-M10, and M15-M16. The total input noise is divided into thermal noise and flicker noise. The input thermal noise is:

Where k is the Boltzmann constant, T is the absolute temperature, and gm is the transconductance of the MOS tube. Input flicker noise as shown in equation (9).

2.3 Quick start low-pass filter circuit

For an ordinary RC filter circuit, the cutoff frequency is as shown in equation (11):

From Equation (10), it can be seen that the better the effect of filtering out noise, the longer the startup time of the RC low-pass filter circuit. In response to this shortcoming, a fast-start RC low-pass filter circuit is proposed. As shown in Figure 4.

M1 is a switch tube, and M2 to M6 work in the deep triode region, which can be considered as a series of resistors in series. At the instant of circuit startup, VCTRL is low, M1 is turned on, and capacitor C0 is charged. When VI=VO, VCTRL is converted to high voltage and M1 is turned off. At this time, the RC filter circuit starts to work. Two of the inverter cascades digitize the output voltage of the error amplifier (EA), allowing VCTRL to more efficiently control the switch M1.

In this design, the value of the capacitor C is in the order of nanometer, and it is difficult to integrate it into the chip [11]. Therefore, the method of externally connecting the capacitor is adopted, and a chip pin is also added correspondingly.

3 Layout and Overall Circuit Simulation 3.1 Layout

Figure 5 shows the layout of the LDO with an overall chip area of ​​approximately 0.03 mm2. Traditional LDOs require only two op amps. This design uses two op amps to meet the actual needs of low noise and fast startup. Although the area of ​​the chip is relatively increased, its performance advantage is sufficient to cover the area. Loss.

3.2 Overall Circuit Simulation

The Cadence Spectre tool was used to test the overall circuit simulation. Figure 6 shows the overall circuit test results of the LDO. Where VDD = 5 V, VOUT outputs a standard supply voltage of 3.3 V. It can be seen from the figure that the circuit startup time is less than 1 ms and the overall circuit has better stability.

As shown in Figure 7, the LNR of the circuit is simulated. VDD varies from 4 to 6 V, and VOUT only changes 16.4 mV.

The calculation shows that its LNR is:

Figure 8 shows the circuit LDR test results. The load current varies from 1 to 30 mA and the output voltage only changes by 0.25 mV. The formula LDR can be calculated as:

Figure 9 shows the simulation results of the output noise. The output noise density (in V/sqrt (Hz)) curve shown in the figure is a squared operation of the output noise power (in V2/Hz).

It is calculated that the noise integral in the range of 1 kHz to 100 kHz (shaded area) is 34.94 μVrms.

4 Conclusion

This paper designs a power supply module for powering the LNA in the MMIC. The performance parameters of the power supply module are shown in Table 1. From the comparison of specific data, it can be seen that the power module designed in this paper integrates a voltage reference source, and has a wide range of output voltage and a small output noise, and all performance parameters meet the requirements of design and application.