Next-generation integrated circuit implementation solution

Magma® Design Automation Co., Ltd. recently introduced the next generation integrated circuit (IC) implementation solution, Talus® 1.2, which can significantly shorten the design cycle of a system-on-chip (SoC). This new Talus system allows engineers to combine crosstalk avoidance, advanced on-chip variation (AOCV) and multi-mode multi-angle (MMMC) analysis functions to achieve 1 to 1.5 million units per day on large designs or circuit modules with 200 to 500 units the design of. Talus has passed the verification of the 40nm node chip and is currently used in complex 28nm designs. With these latest enhancements, Talus is well-prepared to deal with design issues at process nodes below 20 and 20 nanometers.

Talus 1.2 provides a 5-6 times faster design cycle by utilizing faster and precise routing, timing and extraction techniques, and various advanced features, including:
• Talus MX router (Talus MX Router): Provides enhanced global, trace, and detailed routing functions and integrated timing throughout the entire process, eliminating DRC violations.
• Talus MX timing device (Talus MX TImer): Based on Magma's next-generation sign-off timing analysis technology, it realizes faster and more accurate timing analysis.
• Talus MX Extractor (Talus MX Extractor): Based on the latest high-speed, multi-angle extraction technology of Magma, providing faster and more accurate extraction.
• Concurrent MMMC opTImizaTIon (Concurrent MMMC opTImizaTIon): manages 5 times more timing scenarios than traditional solutions, providing 10 times the runtime improvement.
• Advanced On-Chip Variation (AOCV): Ensure tight timing correlation throughout the entire process.
• Crosstalk Avoidance – Detect and correct crosstalk avoidance during optimization and implementation.

"We have achieved fruitful results through the Magma Talus 1.2 platform, which once again proves the correctness of our decision to select this tool to support the needs of our complex chip projects," Exar Executive Vice President and Chief Technology Officer of Engineering Operations George Apostol said. "For our customers, the most important thing is that our devices must support high levels of data traffic without bottlenecks, which requires effective wiring. Talus 1.2 has solved many physical design problems, and the layout and wiring operation The time has also been greatly improved compared to the previous version, which allows us to shorten the development cycle and accelerate the delivery time for customers to provide the next generation of devices to meet the dynamic market demand. "

"Just as the scale and complexity of the design underway are increasing, the pressure on the chip design team to increase productivity is also increasing," said Premal Buch, general manager of the design and implementation business department of WeChat. "According to economics, it is impossible for the design team to expand the scale of the design size, and the design cycle cannot extend the time according to the design size. In order to increase productivity, the tool must provide greater capacity and shorter design cycle At the same time, designers must also be able to improve performance and reduce power consumption in SoC design. Talus 1.2 is such a tool that can provide the shortest design cycle, highest capacity and maximum capacity for the next generation of 28 and 28 nm process node IC design The best quality of results. "

Talus 1.2: Reduced design cycle, excellent design results
The key implementation technology of Talus 1.2 includes the new Talus MX timing and extraction engine. These analysis engines are based on the underlying technology of Magma's next-generation sign-off sequencer-Tekton ™ and sign-off extractor-QCP ™, which is fast, accurate and has a significantly increased capacity, which can be applied throughout Talus 1.2 RTL-to-GDSII processes; they provide new functions such as AOCV and MMMC analysis to ensure close timing correlation throughout the entire process. When used in conjunction with Tekton and QCP, Talus 1.2 can provide sign-level accuracy analysis during design implementation, remove timing ECO, and achieve faster design closure.

For design implementations below 28 and 28 nanometers, it is very common to analyze many different timing scenarios in the design. Magma believes that the timing scenario is equal to the number of process corners x the number of timing patterns. Most solutions only provide the processing power of 5-8 timing scenarios during design implementation. Talus 1.2 can execute concurrent MM / MC on a single device, and can manage 5 times more scenarios than traditional solutions, while also providing 10 times the runtime improvement.

Talus 1.2's new wiring technology can handle various wiring problems below 28 and 28 nanometers, especially in this type of process node, crosstalk management becomes more difficult. If the crosstalk repair is performed at the end of the process, in the best case, at a higher cell area and at higher leakage, then it is too late in time; if it is carried out in the worst case, it may be As a result, the design cannot complete convergence. Talus1.2 can identify and control crosstalk throughout the entire implementation process, providing a more convergent process with far fewer timing surprises, thus avoiding this situation. Unlike other solutions, Talus1.2 can provide a much shorter run time and a more robust design without increasing area and leakage.

Talus 1.2's integration of new technologies allows designers to provide higher performance designs faster. For example, a network company can implement a 40-nanometer design with 2 million cell-level circuits and 10 sign-off scenarios in only two days, combined with comprehensive CCS, MMMC and crosstalk analysis functions.