Special integrated circuit for general pulse generation of power electronic equipment

Various power electronic devices include a pulse generating part that provides control pulses for power electronic devices. Traditional pulse generation circuits based on customized small-scale logic devices have many shortcomings such as complex structure, huge volume, low accuracy, single function and inability to monitor directly. Subsequently, the microprocessor provided a software implementation method for the pulse generation of power electronic equipment, but it was not a good solution. Because microprocessors can only execute programs in a single-threaded manner, they are not suitable for completing pulse generation tasks that require high real-time performance, and cannot implement processing functions such as pulse delay and interlock. When the number of required pulses is large, it is still necessary to design a complex interface circuit for the microprocessor. The portability of the microprocessor-based pulse generation program software is also poor. For these reasons, the power electronic control system hopes that the microprocessor can specialize in the control algorithm of the system, and the pulse generation D * 2 is implemented by using an application specific integrated circuit (ASIC). At present, complex programmable logic devices (CPLD) and Field programmable gate array (FPGA) -based large-scale programmable logic devices and their development technology have made significant progress, which provides a powerful means for implementing pulse-generating ASICs suitable for power electronics applications. Existing research achievements include CPLD-based three-phase rectified pulse trigger circuits, pulse width modulation (PWM) pulse generation that requires microprocessors to prepare pulse width data for it (31), and FPGA-based pulse width modulation including space vector modulation, etc. Pulse generation ASIC of complex algorithm logic. On the basis of drawing on existing achievements, this paper has designed a general-purpose pulse generation ASIC for power electronic equipment with strong intelligence that can meet the needs of various applications. 1 General pulse generation ASIC The main structure is as shown, the internal circuit of the general pulse generation ASIC proposed in this paper is mainly composed of 6 parts: phase control, pulse generation, pulse conditioning, control interface, storage space management and data exchange logic. The phase control part provides step size for pulse generation The interval is the phase scale data of .r. The pulse generation part is composed of a single pulse generation module, a PWM pulse generation module and a PWM pulse data calculation module. The pulse signal generated by the pulse generation part has to undergo pulse conditioning before being output to the chip pins The storage space management part is managed by the controllable status bits and parameter registers The mapping space formed by the address, the static random storage space (SRAM) in the ASIC chip and the non-volatile storage space (NVSRAM) expanded outside the chip. The control interface part provides three kinds of control of analog signal input, key input and digital interface The display function can monitor the working status of the ASIC. The data access between the pulse generating part, the control interface part and the storage space is managed by the data exchange logic.

2 General pulse generation ASIC function module 1 Phase control part The phase control part of the ASIC is based on a fully digital phase-locked loop with a phase-locked range of 0.85kHz and 12kHz at 40 times the frequency. When the ASIC is in the phase-locked synchronization mode, the on-chip phase-locked loop will be used as the second-level phase-locked synchronization system, and a 90-fold phase-locked circuit is also required as the first-level phase-locked synchronization system outside the chip. The frequency scale of 3600 times the frequency-doubled synchronization pulse obtained by the two-stage phase-locking is then subjected to a cycle count from 0 to 3599 to obtain a phase scale of 0.1 *.

If the phase-locked loop in the ASIC is disconnected, and the digitally controlled oscillator of the phase-locked loop is directly controlled by a register parameter in the ASIC, then the phase control part works in the second mode in which the fundamental frequency can be controlled. The third working mode of phase control is online synchronization mode. In this mode, you can choose to use a set of online synchronization signals that are input off-chip directly as the counting pulses and synchronization signals of the phase scale. The online synchronization mode can enable multiple ASICs to send out pulses synchronously, thereby expanding the number of pulse output channels.

2.2 Pulse generation part The pulse generation part is the core of this article ASIC. The single pulse generation module in the pulse generation part can generate a single pulse trigger signal with adjustable start phase and pulse width on each output channel. If the forced trigger logic in this module is enabled, after starting the single pulse output of a channel, the user must first provide a forced trigger signal to make the logic circuit generate a forced pulse before continuing to follow the set starting phase Single pulse is generated normally. This forced trigger function can be applied to the dropout of capacitive devices without pressure drop.

The PWM pulse generation module in the pulse generation section generates PWM pulses based on the pulse data. As shown, the circuit structure contains two sets of the same pulse generating components PWM1 and PWM2. Both components can use their respective bus management modules to sequentially read pulse data from the storage space. Then compare the phase part of the data with the phase scale of the system. When they are the same, modify the pulse output according to the level part in the pulse data to generate a PWM pulse sequence. The two sets of pulse generating components can work independently or alternately under the management of alternate work control logic. In the alternate mode, the PWM1 and PWM2 components will alternately drive the same set of pulse output channels according to the switching command, thereby realizing the ping-pong buffering method of the PWM pulse data. This working mode can make the pulse data calculation update process and the pulse generation process match at any speed, thereby ensuring that the PWM pulse can be safely and dynamically changed.

ASIC also integrates a PWM pulse data calculation module. After the module is selected, the pulse data that meets the format requirements of the pulse generating component is calculated according to the modulation triangle wave and the wave comparison principle. These data will alternately update the corresponding data storage segments of PWM1 and PWM2. After the pulse data of one fundamental wave period is calculated, the calculation module sends a switching command, and the alternate working control logic waits for the PWM pulse generating component in operation to complete the drive of the last pulse data of its corresponding data segment to the output, and then switches another pulse to occur The component starts to work. Thus, the newly started pulse generating component outputs PWM pulses based on the newly updated set of data.

The wave required by the PWM pulse data calculation module is generated from the stored waveform data, its amplitude A * f is fixed, and the fundamental frequency is adjusted by the phase control part of the ASIC. The amplitude of the modulated triangular wave generated by the logic algorithm is variable, and the modulation frequency can be automatically adjusted in a segmented synchronization manner according to F. The maximum amplitude Aa of the modulated triangular wave has two generation forms, which can be expressed by the following formula: a binary control bit.

Therefore, the modulation ratio M = of the PWM is changed. At this time, the ASIC works in the normal modulation ratio controlled mode; when vf-mode is 1, if the control parameter Y is set, Aa will automatically change inversely with the fundamental frequency F. Theoretical analysis shows that when M is proportional, it provides a constant V / F sinusoidal voltage PWM pulse for motor control and other applications.

2.3 Pulse conditioning section The processing of the pulse conditioning section includes the frequency modulation, minimum pulse width adjustment, pulse interlock, and output enable or block. These functions can be enabled or masked, and parameters such as modulation frequency, minimum pulse width and interlock time can be adjusted.

2.4 Control interface part The control interface part includes a single parameter modification module and a digital control interface module. The structure of the single parameter modification module is as shown. It selects the address of the modified parameter through the key signal, and then uses the key operation or the input data after the analog-to-digital conversion to modify the control register and stored data in the ASIC. The analog-to-digital (A / D) conversion input interface matches the 12-bit serial A / D chip MAX187. The display module in the control interface circuit can drive 22 light-emitting diodes (LEDs) and 6 digital tubes to monitor the modified address, register parameters and ASIC working status.

The digital control interface module provides an 8-bit or 16-bit parallel data access bus. By using the busy or idle indication signal BUSY / READY in the bus, the access sequence of the interface can be conveniently matched with microprocessors of different speeds. In the digital control interface, it also has a multiplexed interrupt signal, which is used to notify the external microprocessor of the change in the working state of the ASIC.

2.5 Storage space management part; the storage space includes 3 parts: the mapping space composed of the status control bits and adjustable parameter registers in each function module, high-speed on-chip SRAM, and 8kBNVSRAM expanded outside. Part of the space of NVSRAM is used to store ASIC State control parameters at runtime. When the ASIC is powered on and initialized, the storage space management module reads out the saved state control parameters from the NVSRAM and reassigns them to each function module, thereby restoring the ASIC to the control state before power down. In NVSRAM, the waveform data used for PWM pulse data calculation will also be saved.

2.6 Data exchange logic part The data exchange logic part manages the data access between each functional module and the storage space. When a functional module needs to access data, it must first issue an access request to the data exchange logic. When the data exchange logic completes the current data exchange, it responds to these access requests according to the set priority order, and then performs the corresponding data exchange.

3 Universal pulse generator and its. On the circuit board, the peripheral circuits that assist the operation of the ASIC include the power supply circuit, the 8MHz oscillator that provides the system working clock, the 90-fold phase-locked circuit based on the CD4046, and the interface circuit based on the MAX187 designed for A / D conversion of analog control signals , State setting switch, key input circuit, LED and digital tube display circuit, digital control interface, circuit that uses EPC.2LC20 to load FPGA logic program, etc.

A series of test experiments have been conducted on the designed ASIC chip based on the universal pulse generating device. Experimental results show that: ASIC can complete the aforementioned design functions and achieve the expected performance indicators. The results of a set of output waveforms recorded by the HP54620A logic analyzer when the PWM pulse data calculation module spontaneously generates PWM pulses are given.

It is a three-phase PWM pulse output signal with a phase difference of 12 (T; P2A, P2B and P2C are complementary and interlocked signals of P1A, P1B and P1C, respectively.

In the PWM pulse waveform experiment corresponding to different fundamental frequency Ffl in the V / F constant mode, high frequency modulation is prohibited, the minimum pulse width is 8ps, the interlock delay is 8ps, the wave is a sine wave with an amplitude of 21 *, select V / The working mode of F is constant, that is, vf-mode is 1, and the parameter Y = 20. At this time, the relationship between the modulation ratio M and the fundamental frequency is: 4 Conclusion This article applies large-scale programmable logic devices and their design techniques to power electronics In the technical field, a general-purpose pulse generation ASIC for power electronic equipment with rich functions has been designed. The ASIC is based on the phase angle for pulse generation, which is more intuitive than the traditional pulse width control method. The pulse generation function of the ASIC can meet the needs of a variety of power electronics applications, and the appropriate control pulses can be generated through appropriate function selection and settings. Flexible control interface and status monitoring function can adapt to a variety of practical occasions. The pulse generation device designed based on the ASIC in this paper, on the one hand, serves as a test platform to verify the performance of the ASIC; on the other hand, the device can be directly applied to the research and development of power electronic equipment such as static reactive power compensation, active filter, motor drive, etc. Simplify the design process of the control device hardware. In this paper, each functional module in ASIC is assembleable. Therefore, after the principle experiment is completed, you can further select the corresponding functional module for the application and assemble a new pulse generation ASIC for the actual system. In summary, the development and use of ASIC and pulse generation device It will help promote the digitization and integration of power electronics technology and improve the level of intelligence of power electronics applications.